1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of epitaxially forming materials on transistor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NFET and PFET transistors) represent one important type of circuit elements that substantially determine performance of the integrated circuits. A basic field effect transistor comprises a source region, a gate region and a channel region positioned between the source and drain regions. Such a transistor further includes a gate insulation layer positioned above the channel region and a gate electrode positioned above the gate insulation layer. When an appropriate voltage is applied to the gate electrode, the channel region becomes conductive and current may flow from the source region to the drain region. In many cases, the gate electrodes are made of polysilicon. The basic structure of a field effect transistor is typically formed by forming various layers of material and thereafter patterning those layers of material using known photolithography and etching processes. Various doped regions, e.g., source regions, drain regions, halo regions, etc., are typically formed by performing one or more ion implantation processes through a patterned mask layer using an appropriate dopant material, e.g., an N-type dopant or a P-type dopant, to implant the desired dopant material into the substrate. The particular dopant selected depends on the specific implant region being formed and the type of device under construction, i.e., an NFET transistor or a PFET transistor. During the fabrication of complex integrated circuits millions of transistors, e.g., NFET transistors and/or PFET transistors are formed on a substrate by performing a number of process operations.
The various transistors and other semiconductor devices that are formed on a semiconducting substrate typically have to be electrically isolated from one another so that the devices will operate properly. This electrical isolation is typically achieved by forming various isolation regions, such as so-called shallow trench isolation regions, in the substrate by performing a variety of known processing operations. It is very important that such isolation structures perform their function and thus it is very important that, to the extent possible, such isolation structures be formed without any voids in the insulating material.
Given the advance of the past years in reducing the physical size of transistor devices, device designers have employed a variety of techniques other that physical size reduction in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NFET transistors and create a compressive stress in the channel region for PFET transistors). One performance-enhancing technique that has been employed in manufacturing PFET transistors involves the use of a silicon germanium channel layer. Such a silicon germanium channel layer is typically formed by forming a recess in an active region of a substrate where such a PFET transistor will be formed and thereafter, performing an epitaxial deposition process to form a layer of silicon germanium in the recess. The incorporation of the silicon germanium channel layer enhances the performance of the PFET transistor by bringing the threshold voltage of the device to a desired level (adjusting the work function to the needs of high-k metal gates).
FIGS. 1A-1H depict one illustrative prior art process flow for forming a silicon germanium channel regions for an illustrative PFET transistor. FIG. 1A depicts an illustrative prior art device 100 at an early stage of manufacture. The device 100 is formed above an illustrative bulk substrate 10. As shown therein, a plurality of trenches 12 are formed in the substrate 10 where isolation regions will be formed to define an N-active area 10N and a P-active region 10P. An illustrative pad oxide 14 is formed on the surface 10S of the substrate 10 and a so-called pad nitride layer 16 is formed on the pad oxide layer 16. The layers 14, 16 may be formed using traditional tools and techniques. The trenches 12 may be formed by performing one or more known etching techniques through a patterned mask layer (not shown), e.g., a photoresist mask.
Next, as shown in FIG. 1B, a trench isolation structure 18 is formed in the trenches 12 using traditional techniques. For example, a layer of trench isolation material, e.g., silicon dioxide, may be blanket-deposited across the substrate 10 and a chemical mechanical polishing (CMP) process may be performed (using the pad nitride layer 16 as a polish stop) to remove the excess material positioned outside of the trenches 12, thereby resulting in the shallow trench isolation structures 18.
As device dimensions have decreased over recent years and technology generations, the space between adjacent transistors has also decreased. This increased density has, in some cases, made it difficult to form void-free isolation structures 18. In an effort to overcome this problem, after the trenches 12 are initially formed, at least some prior art techniques included the step of “pulling-back” the nitride pad layer 16, as indicated by the reference number 17 in FIG. 1A. This was typically accomplished by performing an etching process using an etchant like, for example, H3PO4. In effect, this “pull-back” was an attempt to make the opening of the trenches 12 wider so that filling of the trenches 12 would be easier, with the hope of reducing the creation of undesirable voids in the final shallow trench isolation structures 18.
After the trench isolation structures 18 are formed, an etching process is performed to remove the pad nitride layer 16, as shown in FIG. 1C. Then a shown in FIG. 1D, a hard mask 20 is deposited on the device 100. The hard mask 20 may be a layer of silicon dioxide or silicon nitride having a thickness of about 20-30 nm, and it may be formed by performing a chemical vapor deposition (CVD) process. A mask layer 22, e.g., a photoresist mask, is formed that covers the N-active area 10N and exposes the P-active area 10P for further processing.
Next, as shown in FIG. 1E, the photoresist mask 22 is used during an etching process that is performed to remove the hard mask 20 and the pad oxide 14 in the exposed P-active region 10P. Typically, this is accomplished by performing a wet etching process. The oxide hard mask 20 and the oxide shallow trench isolation structures 18 tend to have higher wet etching rates than does the pad oxide layer 14. As indicated, portions of the shallow trench isolation structures 18 are removed during this etching process, as indicated by the reference number 18R. Additionally, a portion of the pad oxide layer 14 is, in effect, protected by the over-hang of the shallow trench isolation regions 18 during the etching process. As a result, when the etching process is completed, there tends to be pad oxide remnants 14R, for example in the form of a ring in some cases that remains on the P-active region 10P. FIG. 1F is a plan view of the P-active region 10P depicting the pad oxide remnants 14R in the form of a ring. The pad oxide remnants 14R may not be continuous as depicted in FIG. 1F, and it may have a width (when viewed in FIG. 1F) of about 6-9 nm, depending upon the particular application.
Next, as shown in FIG. 1G, an etching process is performed to define a recess 26 in the P-active region 10P. Ultimately, a silicon germanium channel material for a PFET transistor will be formed in the recess 26. Unfortunately, the pad oxide remnants 14R tends to act as a mask during the etching of the substrate 10 thereby resulting in protrusion or “teeth” 30 of substrate 10 in the P-active area 10P. Prior art efforts to remove the pad oxide remnants 14R also raise additional issues. For example, if a cleaning process is performed for a sufficient duration to completely remove the pad oxide remnants 14R, the shallow trench isolation structure 18 is also attacked, thereby tending to reduce the effectiveness of the isolation structure 18. If the cleaning process is reduced so as to not excessively attack the isolation structures 18, then the surface 10S of the P-active region 10P may be insufficiently cleaned and/or, in a worst-case scenario, portions of the pad oxide remnants 14R remain in place and effectively serve as a mask during the etching process that forms the recess 26. This latter masking effect is depicted in FIG. 1G and results in the formation of the undesirable protrusions 30 discussed above.
As shown in FIG. 1H, the next process involves the formation of a layer of channel semiconductor material 32 in the recess 26. Prior to forming the channel semiconductor material 32, the device 100 was typically subjected to a heating or baking process, e.g., about 800° C. for a duration of about 30-60 minutes using about 4 slm of hydrogen (H2). In one illustrative example, the channel semiconductor material 32 is a layer of silicon germanium that is formed by performing an expitaxial deposition process. Unfortunately, the presence of the protrusions 30 causes the ends 34 of the semiconductor material 32 to take on an irregular shape—more or less a facetted shaped—proximate the border of the P-active area 10P. The actual shape of the irregularly-shaped ends 34 depends upon factors such as the amount of loss of the isolation structures 18 and the magnitude and shape of the protrusions 30. These irregularly-shaped ends 34 are not beneficially to the performance of the PFET transistor that will ultimately be formed in and above the P-active region 10P because, to a great extent, the threshold voltage of the PFET transistor is determined by the thickness of the semiconductor material 34. Thus, thickness variations in the channel semiconductor material is generally not desired and such thickness variations may lead to reduced performance capabilities of the PFET transistor.
The present disclosure is directed to various methods of forming expitaxially formed layers of material and semiconductor devices incorporating such layers of materials that may at least reduce or eliminate one or more of the problems identified above.